(a) Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT) panel for a liquid crystal display (LCD) by photolithography and a photolithography method for fabricating thin films, especially to a method to reduce the number of photolithography steps in manufacturing a TFT panel for an LCD.
(b) Description of the Related Art
An LCD (liquid crystal display) is one of the most popular FPDs (flat panel displays). The LCD has two panels having two kinds of electrodes for generating electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
The field-generating electrodes may be formed at each of the panels, or at one of the panel. The panel having at least one kind of the electrodes has switching elements such as thin film transistors.
In general, a TFT (thin film transistor) array panel of an LCD includes a plurality of pixel electrodes and TFTs controlling the signals supplied to the pixel electrodes. The TFT array panel is manufactured by photolithography using a plurality of photomasks, and it goes through five or six photolithography steps to complete the TFT array panel. The high costs and long time that the photolithography process bears makes it desirable to reduce the number of the photolithography steps.
Several manufacturing methods of LCDs using only four photolithography steps are suggested such as in Korean Patent Application No. 1995-189 ('189). The corresponding U.S. patent is U.S. Pat. No. 5,818,551. In the meantime, since an LCD actually requires wires for transmitting electric signals to the TFTs and wire pads for receiving the signals from outside, the full process to complete a TFT array panel requires the step of forming the pads. However, '189 does not disclose how to form the pads.
Other conventional method of manufacturing a TFT array panel using four photolithography steps is disclosed in “A TFT Manufactured by 4 Masks Process with New Photolithography (Chang Wook Han et al., Proceedings of The 18th International Display Research Conference Asia Display 98, pp. 1109–1112, 1998. 9.28–10.1).
Meanwhile, a storage capacitor for sustaining the voltage applied to a pixel is generally provided in the TFT array panel, and the storage capacitor includes a storage electrode and a portion of a pixel electrode as well as a passivation layer interposed therebetween. The storage electrode is made of the same layer as a gate wire, and the portion of the pixel electrode is formed on the passivation layer. The storage electrode is covered with a gate insulating layer, a semiconductor layer and a passivation layer, and most portion of the pixel electrode is formed directly on the substrate in Han et al. Therefore, the pixel electrode should step up the triple layers of the gate insulating layer, the semiconductor layer and the passivation layer, in order to overlap the storage electrode. It may cause a disconnection of the pixel electrode near the high step-up area.
In the meantime, as shown in '189, the conventional photolithography process uses a photoresist (PR) layer. The conventional photoresist layer is exposed to light through a photomask and divided into two sections, one exposed to the light and the other not exposed. The development of the photoresist layer forms the PR pattern having a uniform thickness with the PR layer exposed to the light removed. Accordingly, the etched thickness of the layers under the PR pattern is also uniform. However, Han et al. uses a photomask having a grid, which lowers the amount of light reaching the portion of a positive PR layer thereunder, to form a PR pattern having thinner portions than the other portions. The different thickness of the PR pattern produces the different etching depth of the underlying layers.
Therefore, Han et al. has a problem in forming the grid throughout a wide region, and it is hard to make the etching depth uniform under the grid region, even though the grid is formed throughout the wide region.
U.S. Pat. Nos. 4,231,811, 5,618,643, and 4,415,262 and Japanese patent publication No. 61-181130, etc., which disclose similar methods as Han et al., have the same problem.